Magnetoresistive random access memory (MRAM) is a non-volatile memory technology where data is stored based on magnetization polarities of bit cells. In contrast to conventional RAM technologies which store data as electric charges or current flows, MRAM uses magnetic elements. A magnetic tunnel junction (MTJ) which is conventionally used as a storage element or bit cell for MRAM technology, can be formed from two magnetic layers, each of which can hold a magnetic moment, separated by an insulating (tunnel barrier) layer. Conventionally, the fixed layer is set to a particular polarity. The free layer's polarity is free to change to match that of an external magnetic field that can be applied. A change in the polarity of the free layer will change the resistance of the MTJ bit cell. For example, when the magnetization polarities are aligned or “parallel,” a low resistance state exists, which corresponds to a logical “0”. When the magnetization polarities are not aligned or are “anti-parallel,” a high resistance state exists, which corresponds to a logical “1”.
While the MRAM offers many benefits in terms of cost and area, the read access speeds for MRAM remain significantly lower than the read access speeds for conventional non-volatile memories such as static random access memory (SRAM). The read process for an MRAM generally involves determining the resistance of a particular bit cell. The resistance of a bit cell is variable, based on the alignment of the free layer and the fixed layer of an MTJ bit cell as noted above. A same or similar current is passed through an MTJ bit cell as well as a reference cell of known resistance, where the reference cell is usually set to a resistance which corresponds to a mid-way resistance between that of a logical “1” and a logical “0”. The voltage developed across the MTJ bit cell is compared to the voltage developed across the reference cell. A higher voltage across the MTJ bit cell implies that the data stored in the MTJ is “1” and a lower voltage across the MTJ bit cell implies that the data stored in the MTJ is “0.” The above general process is explained in further detail with reference to FIG. 1 below.
FIG. 1 illustrates a conventional MRAM system 100 which includes MTJ bit cells 136a and 136b of variable resistance. MTJ bit cells 136a-b are addressable by a particular row and column address. MTJ bit cells 136a-b belong to a row which is selected when word line WL 130 is high. MTJ bit cells 136a-b are one of several MTJ bit cells (not shown) on the same row, and as such, column muxes (not shown) are used to select MTJ bit cells 136a-b from within the row. For this column selection, the control signal read select RDSEL 128 is used, which is based on the column address for MTJ bit cells 136a-b. In conventional designs, WL 130 is asserted first as the row address can be decoded faster. RDSEL 128 is asserted after a time delay following the assertion of WL 130 as it takes longer in conventional designs to decode the column address.
In the illustrated example in FIG. 1, MTJ bit cell 136a is shown to have a resistance corresponding a parallel alignment and has a logical “0” stored therein, and MTJ bit cell 136b holds a resistance corresponding to an anti-parallel alignment and has a logical “1” stored therein. Reference cells Rp 138a and Rap 138b are provided, which are MTJ bit cells programmed to known resistance/logical values of “0” and “1” respectively. Reference cells Rp 138a and Rap 138b, when coupled in parallel generate to generate an effective resistance, say Rref.
A read operation for MRAM system 100 is now discussed with reference to the timeline provided in FIG. 1B. Signal voltage values are shown on the Y-axis and time is shown on the X-axis. Word line WL 130 is asserted at time t101, which turns on n-channel metal oxide semiconductor (NMOS) transistors 140a-b and 142a-b. After a time delay, read select RDSEL 128 is asserted at time t102, which turns on NMOS transistors 132a-b and 134a-b. In order to ensure that the resistances (data values) stored in MTJ bit cells 136a-b are sensed correctly and compared with the equivalent resistance Rref of the reference cells, the read operation begins by equalizing all nodes. Particularly, equalization signal 118 is turned on before commencing the read operation (e.g., at time 0), which turns on the equalization/pass transistors 120a and 120b, which remain on until equalization signal 118 is deactivated at time t104.
The signal VGCLAMP 126 (not shown in FIG. 1B) when turned on, causes NMOS transistors 122a-b and 124a-b to be turned on, which supplies the same current through MTJ bit cells 136a-b and the reference cells Rp 138a and Rap 138b. The gate terminals of load p-channel metal oxide semiconductor (PMOS) transistors 114a-b are connected to their respective drain terminals in order to form diodes, which creates a voltage Vref at node 116. This voltage Vref 116 is based on the effective resistance Rref. On the other hand, load PMOS transistors 112a and 112b generate voltages at nodes COUT0 106a and COUT1 106b based on the resistances of MTJ bit cells 136a and 136b respectively. Initially, Vref 116 and COUT0/1 106a-b are equalized to an initial voltage value v101 based on equalization signal 118 being asserted. Once RDSEL 128 is asserted, at time t103, Vref 116 and COUT0/1 106a-b start to change and move closer to a midpoint voltage value v102. At time t104, equalization signal 118 is deactivated. At this time, Vref will reach its reference value of v103, based on the current flowing through Rref and the diode created at PMOS load transistors 114a-b. The voltage at COUT0 106a will start to voltage v105 which is lower voltage than v103 due to the lower resistance corresponding to the logical “0” stored in MTJ bit cell 136a. Similarly, COUT1 106b will increase to voltage v104 which is a higher voltage than v103 due to the higher resistance corresponding to the logical “1” stored in MTJ bit cell 136b. 
At time t107, voltage sense amplifiers (VSAs) 104a and 104b are enabled by sense amplifier enable signal SAEN 103. VSAs 104a-b are used to amplify the above voltage differences −ΔV1=v103−v105 and +ΔV2=v104−v103. The amplified voltage differences lead to sensing the logical value stored in the MTJ bit cells 136a and 136b as “0” and “1” respectively at output nodes GDOUT0 102a and GDOUT1 102b at time t108.
With reference to FIG. 1C, an example simulation of sample signals during a read operation on MRAM system 100 is depicted. With combined reference to FIGS. 1B-C, it is seen that it takes a time delay from when WL 130 is asserted at time t101 to when Vref 116 settles to voltage v103 at time t105. This settling time is required for Vref 116 to be stable and provide a correct reference for sensing the resistance values stored in MTJ bit cells 136a-b. This settling time is shown to be as high as 2 ns in FIG. 1C. It takes an additional time after time t105 till time t107, where SAEN 103 is asserted and eventually GDOUT0/1 102a-b generate stable read values of “0” and “1” respectively. In FIG. 1C, this time taken from the settling of Vref 116 at time t104 to time t107 when SAEN 103 is asserted is also shown to be 2 ns. Thus, it is seen that it takes approximately the same amount of time to sense the data stored in the MTJ bit cells after Vref settles, as the time it takes for Vref to settle from when WL 130 is asserted.
Accordingly, the Vref settling time (e.g., t104-t101) is a major contributor to the read access time for MRAM system 100. In comparison, SRAM systems do not require a similar Vref settling time for reading SRAM bit cells. In general MRAM read access speed is slower than that of SRAM. The Vref settling time further deteriorates the MRAM read access speeds. Accordingly, there is a need to improve the read access speeds for MRAM systems.